Graph theoretic algorithm for VLSI regular structures folding

Please use this identifier to cite or link to this item: http://edoc.bseu.by:8080/handle/edoc/85030

Title:	Graph theoretic algorithm for VLSI regular structures folding
Authors:	Cheremisinova, L.
Keywords:	computational costs;graph theoretic;one-dimensional unconstrained simple;вычислительные затраты
Issue Date:	2001
Publisher:	Белорусский государственный экономический университет
Language:	Английский
Type:	Article
Citation:	Cheremisinova, L. Graph theoretic algorithm for VLSI regular structures folding / L. Cheremisinova // Информационные сети, системы и технологии = Information Networks, Systems and Technologies : в 3 кн. Кн.1 : Труды международной конференции ICINASTe'2001, Минск, 2-4 октября 2001 г. : на англ. яз. / Ред.: А.Н. Морозевич [и др.]. - Мн. : БГЭУ, 2001. - С. 98-102.
Abstract:	The problem under consideration is to reduce the area of the layout of regular VLS structures by means of their folding. Some results of cutting down exhaustive computational efforts on the search for the optimal regular structures folding have been described. An efficient graph theoretic algorithm for one-dimensional unconstrained simple folding is presented.
URI:	http://edoc.bseu.by:8080/handle/edoc/85030
ISBN:	985-426-692-3
Appears in Collections:	Информационные сети, системы и технологии = Information Networks, Systems and Technologies

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